1. Field of Invention
The present invention relates to a slew rate enhancement circuit. More particularly, the present invention relates to the slew rate enhancement circuit which is compact and occupies small chip area.
2. Description of Related Art
To achieve a high slew rate, when an operational amplifier (“OPAMP”) drives a heavy load. Many techniques are used to enhance the slew rate, such as: increasing operating current of OPAMP, reducing a compensation capacitor, or being connected to an error amplifier. Except for the high slew rate, a lost of disadvantages such as a high operating current and a stability degradation for original OPAMP, a large chip area, complexity of circuit design, noise and offset are introduced from the followed error amplifiers.
FIG. 1 illustrates a high slew rate amplifier according to a prior art. The circuit in FIG. 1 includes an OPAMP 102, error amplifiers 104, 106 and a push-pull output stage 112. The push-pull output stage includes a P-type Metal Oxide Semiconductor (“PMOS”) transistor 108 and an N-type Metal Oxide Semiconductor (“NMOS”) transistor 110. The inverting inputs of the error amplifier 104 and the error amplifier 106 are connected to the output of the OPAMP 102 at a node N11. The non-inverting inputs of the error amplifier 104 and the error amplifier 106 are connected to a load at a node N12. The loop of connection between an output of the error amplifier 104 and the gate of the PMOS transistor 108, and the loop of connection between the drain of the PMOS transistor 108 and the non-inverting input of the error amplifier 104 formed a negative feedback loop. Likewise, the loop of connection between the output of the error amplifier 106 and the gate of the NMOS transistor 110, and the loop of connection between the drain of the NMOS transistor 110 and the non-inverting input of the error amplifier 106 also formed a negative feedback loop. The node N11 and the loop including node N12 construct a virtual short loop. The virtual short loop and both of the negative feedback loops are applied to control the PMOS transistor 108 to push current to the load or to control the NMOS transistor 110 to pull current from the load.
The error amplifier 104 and the error amplifier 106 are applied to monitor the output signals of the OPAMP 102. When a non-inverting input Vin10 is not equal to an inverting input Vout10, the error amplifier 104 and the error amplifier 106 turn on the PMOS transistor 108 to push a current to the load, or turn on the NMOS transistor 110 to pull a current from the load. On the other hand, when the signal Vin10 is equal to the signal Vout10, the PMOS transistor 108 and the NMOS transistor 110 work under the DC bias condition.
In general, the circuit of FIG. 1 is usually applied to a buffer amplifier. In order to provide a larger current from the PMOS transistor 108 and the NMOS transistor 110, aspect ratios of the PMOS transistor 108 and the NMOS transistor 110 should be as large as possible, but a static operating current is also increased according to the aspect ratio. Furthermore, a real circuit on a chip is more complicated than FIG. 1, since the error amplifier 104 is constructed by at least 5 pieces of Metal Oxide Semiconductor (“MOS”) transistors, and so dose the error amplifier 106. If the Miller Compensation is applied to compensate the pole/zero location shifts, the other two compensation capacitors are introduced into the circuit of FIG. 1. If the offset voltage, symmetry of layout, cross distortion, linearity, bandwidth and noise of and from the error amplifier 104 and error amplifier 106 are calibrated, additional circuits will be added to the circuit of FIG. 1. Therefore, the manufacturing of the circuit of FIG. 1 on a chip will occupy a huge chip area and consume a high static operating current of the original OPAMP.